1. Technical Field
Embodiments of the invention relate generally to memory devices, and more particularly, but not exclusively, to performing refreshes for a dynamic random access memory (DRAM).
2. Background Art
Memory devices are ubiquitous for a variety of computer device applications. Dynamic random access memory (DRAM) is commonly used as working memory in computing devices. The working memory is often volatile (it loses state if power is interrupted to the system), and provides temporary storage for data and programs (code) to be accessed and executed by the system processor(s).
There are multiple types and variations of DRAM, one example being synchronous DRAM (SDRAM). Being dynamic, DRAM requires continuous or regular refreshing of the data bits stored in the memory device. The refreshing is generally controlled by a memory controller, which periodically accesses data bits of the memory device. Typically, memory cells in a DRAM are each constructed from a single transistor and a single capacitor. Such memory is called dynamic because its data decays and becomes invalid due to various leakage current paths to surrounding cells and to the substrate. Therefore, to keep the data in the cells valid, each memory cell is periodically refreshed. Data in a DRAM cell array is refreshed every time it is read out of the cell array into the sense amplifiers and subsequently rewritten into the cell. Memory that is not read is refreshed by a specific refresh operation.
The memory controller is responsible for periodically performing refresh maintenance operations on the memory cell array. Every row of the memory array needs to be refreshed before the data in the row decays to an invalid state. During self-refresh mode the DRAM device is responsible for performing the refreshes.
Various factors, such as temperature or process variation, can impact the ability of dynamic random access memory technology to maintain a valid charge in each memory cell over a specified refresh interval. The time spent refreshing DRAM continues to grow with DRAM densities, which impacts isochronous bandwidth and worst case latency. Isochronous bandwidth refers to bandwidth guarantees on the memory subsystem.